Реверсивный сдвиговый N разрядный регистр на VHDL

library ieee;
use ieee.std_logic_1164.all;
entity SOE is
generic (
    n : integer := 4 );
port(
D : in std_logic;
Q : out std_logic;
L, C : in std_logic);
end SOE;
 
architecture beh of SOE is
signal T : std_logic_vector(n downto 0);
begin
  s: for i in n-1 downto 0 generate
begin
process (C)
begin
if C'event and C='1' and L='1' then  
  T(i+1) <= D;
   Q <= T(i);
elsif C'event and C='1' and L='0' then  
  T(i) <= D;
   Q <= T(i+1);
end if;  
end process; 
end generate;
 end beh;

library ieee;
use ieee.std_logic_1164.all;
entity RUS is
  generic (
      n : integer := 4);
  end RUS;
 
 
architecture BLR of RUS is
component SOE 
   generic (
      n : integer);
    port (
    D : in std_logic;
    Q : out std_logic;
    L, C : in std_logic);
    end component;
   
   
  signal Q: std_logic:='0';
  signal D: std_logic:='1';
  signal T: std_logic_vector (n downto 0);
  signal L: std_logic:='0';
  signal C: std_logic:='0';
  
begin
 
  DUT1: SOE
     generic map (
      n => n)
    port map (
      D=>D,
        Q=>Q,
        L=>L,
        C=>C);
        
    D <= not D after 1000 ns;
    L <= not L after 120 ns;
    C <= not C after 10 ns;
    end architecture BLR;