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Windows VirtualBox - this kernel requires an x86-64 CPU26.02.2021, 10:18. Показов 10145. Ответов 14
Метки virtualbox (Все метки)
Прежде всего - да, я понимаю, что это FAQ. И тем не менее. Не могу запустить х64 guest с этой ошибкой. Хост - windows 10 x64. Компьютер новый, ранее на нём VB не запускал. Процессор AMD, SVM mode в EFI включен. Hyper-V вроде бы выключен, в "комонентах windows" галки не стоят. Эту страницу https://forums.virtualbox.org/... =1&t=62339 читал и выполнил рекомендации, которые мог. Device Guard через gui недоступен, в реестре установил KLM|SYSTEM|CurrentControlSet|Control|DeviceGuard|EnableVirtualizationBasedSecuri ty|Enabled == 0. Что ему ЕЩЁ надо?
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(| 26.02.2021, 10:18 | |
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Ответы с готовыми решениями:
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This kernel requires the following features not present on the cpu pae ERROR: x86 emulation currently requires hardware acceleration Ошибка x86 emulation currently requires hardware acceleration |
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Native x86
 5635 / 3375 / 957
Регистрация: 13.02.2013
Сообщений: 10,701
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| 26.02.2021, 19:03 | 4 |
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Ну так очевидно, что гость представляет собой 64-битную систему, а инстанс виртуальной машины настроен на запуск 32-битной. Смените тип опереационной системы в настройках экземпляра виртуальной машины (Общие -> Основные -> Версия -> Выбрать систему с припиской "(64-bit)").
Если таких версий нет, то убедитесь, что у вас 64-битная основная система, что в BIOS включена виртуализация (VT-x для Intel или SVM для AMD). Ну и что у вас основная система уже не запущена из-под гипервизора.
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| 28.02.2021, 22:09 [ТС] | 6 |
Сообщение от quwy
Сообщение от quwy
Сообщение от dondublon
Сообщение от quwy
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| 02.03.2021, 10:32 [ТС] | 10 |
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quwy, спасибо за участие.
запустил ubuntu-based linix, с пометкой legacy, 32 bit, работает. Информация по процессору: Кликните здесь для просмотра всего текста
AMD Ryzen 7 3700X 8-Core Processor AMD64 Family 23 Model 113 Stepping 0, AuthenticAMD Microcode signature: 00000000 HTT * Multicore CET - Supports Control Flow Enforcement Technology Kernel CET - Kernel-mode CET Enabled User CET - User-mode CET Allowed HYPERVISOR - Hypervisor is present VMX - Supports Intel hardware-assisted virtualization SVM * Supports AMD hardware-assisted virtualization X64 * Supports 64-bit mode SMX - Supports Intel trusted execution SKINIT * Supports AMD SKINIT SGX - Supports Intel SGX NX * Supports no-execute page protection SMEP * Supports Supervisor Mode Execution Prevention SMAP * Supports Supervisor Mode Access Prevention PAGE1GB * Supports 1 GB large pages PAE * Supports > 32-bit physical addresses PAT * Supports Page Attribute Table PSE * Supports 4 MB pages PSE36 * Supports > 32-bit address 4 MB pages PGE * Supports global bit in page tables SS - Supports bus snooping for cache operations VME * Supports Virtual-8086 mode RDWRFSGSBASE * Supports direct GS/FS base access FPU * Implements i387 floating point instructions MMX * Supports MMX instruction set MMXEXT * Implements AMD MMX extensions 3DNOW - Supports 3DNow! instructions 3DNOWEXT - Supports 3DNow! extension instructions SSE * Supports Streaming SIMD Extensions SSE2 * Supports Streaming SIMD Extensions 2 SSE3 * Supports Streaming SIMD Extensions 3 SSSE3 * Supports Supplemental SIMD Extensions 3 SSE4a * Supports Streaming SIMDR Extensions 4a SSE4.1 * Supports Streaming SIMD Extensions 4.1 SSE4.2 * Supports Streaming SIMD Extensions 4.2 AES * Supports AES extensions AVX * Supports AVX instruction extensions AVX2 * Supports AVX2 instruction extensions AVX-512-F - Supports AVX-512 Foundation instructions AVX-512-DQ - Supports AVX-512 double and quadword instructions AVX-512-IFAMA - Supports AVX-512 integer Fused multiply-add instructions AVX-512-PF - Supports AVX-512 prefetch instructions AVX-512-ER - Supports AVX-512 exponential and reciprocal instructions AVX-512-CD - Supports AVX-512 conflict detection instructions AVX-512-BW - Supports AVX-512 byte and word instructions AVX-512-VL - Supports AVX-512 vector length instructions FMA * Supports FMA extensions using YMM state MSR * Implements RDMSR/WRMSR instructions MTRR * Supports Memory Type Range Registers XSAVE * Supports XSAVE/XRSTOR instructions OSXSAVE * Supports XSETBV/XGETBV instructions RDRAND * Supports RDRAND instruction RDSEED * Supports RDSEED instruction CMOV * Supports CMOVcc instruction CLFSH * Supports CLFLUSH instruction CX8 * Supports compare and exchange 8-byte instructions CX16 * Supports CMPXCHG16B instruction BMI1 * Supports bit manipulation extensions 1 BMI2 * Supports bit manipulation extensions 2 ADX * Supports ADCX/ADOX instructions DCA - Supports prefetch from memory-mapped device F16C * Supports half-precision instruction FXSR * Supports FXSAVE/FXSTOR instructions FFXSR * Supports optimized FXSAVE/FSRSTOR instruction MONITOR * Supports MONITOR and MWAIT instructions MOVBE * Supports MOVBE instruction ERMSB - Supports Enhanced REP MOVSB/STOSB PCLMULDQ * Supports PCLMULDQ instruction POPCNT * Supports POPCNT instruction LZCNT * Supports LZCNT instruction SEP * Supports fast system call instructions LAHF-SAHF * Supports LAHF/SAHF instructions in 64-bit mode HLE - Supports Hardware Lock Elision instructions RTM - Supports Restricted Transactional Memory instructions DE * Supports I/O breakpoints including CR4.DE DTES64 - Can write history of 64-bit branch addresses DS - Implements memory-resident debug buffer DS-CPL - Supports Debug Store feature with CPL PCID - Supports PCIDs and settable CR4.PCIDE INVPCID - Supports INVPCID instruction PDCM - Supports Performance Capabilities MSR RDTSCP * Supports RDTSCP instruction TSC * Supports RDTSC instruction TSC-DEADLINE - Local APIC supports one-shot deadline timer TSC-INVARIANT * TSC runs at constant rate xTPR - Supports disabling task priority messages EIST - Supports Enhanced Intel Speedstep ACPI - Implements MSR for power management TM - Implements thermal monitor circuitry TM2 - Implements Thermal Monitor 2 control APIC * Implements software-accessible local APIC x2APIC - Supports x2APIC CNXT-ID - L1 data cache mode adaptive or BIOS MCE * Supports Machine Check, INT18 and CR4.MCE MCA * Implements Machine Check Architecture PBE - Supports use of FERR#/PBE# pin PSN - Implements 96-bit processor serial number PREFETCHW * Supports PREFETCHW instruction Maximum implemented CPUID leaves: 00000010 (Basic), 80000020 (Extended). Maximum implemented address width: 48 bits (virtual), 48 bits (physical). Processor signature: 00870F10 Logical to Physical Processor Map: **-------------- Physical Processor 0 (Hyperthreaded) --**------------ Physical Processor 1 (Hyperthreaded) ----**---------- Physical Processor 2 (Hyperthreaded) ------**-------- Physical Processor 3 (Hyperthreaded) --------**------ Physical Processor 4 (Hyperthreaded) ----------**---- Physical Processor 5 (Hyperthreaded) ------------**-- Physical Processor 6 (Hyperthreaded) --------------** Physical Processor 7 (Hyperthreaded) Logical Processor to Socket Map: **************** Socket 0 Logical Processor to NUMA Node Map: **************** NUMA Node 0 No NUMA nodes. Logical Processor to Cache Map: **-------------- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 **-------------- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 **-------------- Unified Cache 0, Level 2, 512 KB, Assoc 8, LineSize 64 ********-------- Unified Cache 1, Level 3, 16 MB, Assoc 16, LineSize 64 --**------------ Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 --**------------ Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 --**------------ Unified Cache 2, Level 2, 512 KB, Assoc 8, LineSize 64 ----**---------- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 ----**---------- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 ----**---------- Unified Cache 3, Level 2, 512 KB, Assoc 8, LineSize 64 ------**-------- Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ------**-------- Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ------**-------- Unified Cache 4, Level 2, 512 KB, Assoc 8, LineSize 64 --------**------ Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64 --------**------ Instruction Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64 --------**------ Unified Cache 5, Level 2, 512 KB, Assoc 8, LineSize 64 --------******** Unified Cache 6, Level 3, 16 MB, Assoc 16, LineSize 64 ----------**---- Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64 ----------**---- Instruction Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64 ----------**---- Unified Cache 7, Level 2, 512 KB, Assoc 8, LineSize 64 ------------**-- Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64 ------------**-- Instruction Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64 ------------**-- Unified Cache 8, Level 2, 512 KB, Assoc 8, LineSize 64 --------------** Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64 --------------** Instruction Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64 --------------** Unified Cache 9, Level 2, 512 KB, Assoc 8, LineSize 64 Logical Processor to Group Map: **************** Group 0
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Native x86
5635 / 3375 / 957
Регистрация: 13.02.2013
Сообщений: 10,701
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| 12.03.2021, 01:04 | 15 |
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Значит дело не в железе и не в системе, какой-то глюк виртуалбокса.
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| 12.03.2021, 01:04 | |
| 12.03.2021, 01:04 | |
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Помогаю со студенческими работами здесь
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Ошибка x86 emulation currently requires hardware acceleration в android studio
Ошибка в Android Studio: "x86 emulation currently requires hardware acceleration" Отладка UserControl для x86 платформы и CPU
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